The Zilog Z80 instruction set by group, with opcode bytes, length, T-states, and flags. Register-family instructions use the bit-field encoding below, the way the Z80 encodes them. Type to filter.
registerr = B 0, C 1, D 2, E 3, H 4, L 5, (HL) 6, A 7 16-bit pairdd / ss = BC 0, DE 1, HL 2, SP 3 · qq (push/pop) = BC, DE, HL, AF conditioncc = NZ 0, Z 1, NC 2, C 3, PO 4, PE 5, P 6, M 7 · b = bit number 0–7
patterns like 80+r or 40+8·b+r mean: take the base byte and add the encoded field(s).
Instruction
Opcode
Len
T
Flags
Notes
Flags shown are S Z H P/V N C; · = unaffected, a letter = updated, 0/1 = forced. (HL) forms cost more T-states than the register forms (noted). A DD or FD prefix turns HL into IX or IY and turns (HL) into (IX+d)/(IY+d), adding a byte and roughly 8–12 T-states. Branch and block timings show taken / not-taken where they differ.